КФУ. Карточка публикации. A Configurable IP Core for Calculating the Integer Square Root for Serial and Parallel Implementations in FPGA

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A CONFIGURABLE IP CORE FOR CALCULATING THE INTEGER SQUARE ROOT FOR SERIAL AND PARALLEL IMPLEMENTATIONS IN FPGA

Форма представления

Статьи в зарубежных журналах и сборниках

Год публикации

2022

Язык

английский

Авторы, сотрудники КФУ

Мосин Сергей Геннадьевич, автор

Библиографическое описание на языке оригинала

Matyukha V, Voloshchuk S, Mosin S., A Configurable IP Core for Calculating the Integer Square Root for Serial and Parallel Implementations in FPGA//Electronics (Switzerland). - 2022. - Vol.11, Is.15. - Art. №2335.

Аннотация

The development of digital technologies is in many ways associated with an improvement of integrated technologies, microelectronic components, and the capabilities of hardware accelera-tion of the most computationally complex operations. Field-programmable gate arrays (FPGAs) are actively used for prototyping or the small-scale production of special purpose digital signal processing (DSP) devices. The implementation of DSP algorithms is variative in nature and affects important indicators of a produced device, such as the accuracy of the numerical solution, per-formance, structural/functional complexity, etc. The architectural features of the FPGA can be used for choosing an effective DSP algorithm in the form of solving the multicriteria discrete optimi-zation problem. This paper analyzes and selects an effective algorithm for calculating the integer square root, which is one of the most frequently used digital signal processing operations. A behavioral model based on a non-restoring algorithm is presented. The SystemVerilog description of the module for calculating the square root, presented in the form of a universal configurable IP core, has been developed and synthesized. The configuration allows one to change the width of the input data bus and select the serial or parallel processing mode for scalar or vector data. The results of testing and comparison of the obtained characteristics with the corresponding Xilinx Cordic IP core are presented. The field test of the proposed IP core implemented in the Xilinx FPGA SOC xc7z045ffg900-2 has demonstrated the gain in the maximum system frequency at 174 MHz in the sequential mode with a 48-bit input bus and 169 MHz in the pipelined mode at a reduction of both the structural complexity and the number of used FPGA internal resources in comparison with the Xilinx Cordic IP core.

Ключевые слова

integer square root, non-restoring algorithm, FPGA design, pipelined data processing

Название журнала

Electronics (Switzerland)

URL

https://www.scopus.com/inward/record.uri?eid=2-s2.0-85136799090&doi=10.3390%2felectronics11152335&partnerID=40&md5=1a3ede97935ba9a5ea4b249bc9a02784

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https://repository.kpfu.ru/?p_id=270395

Полная запись метаданных

Поле DC	Значение	Язык
dc.contributor.author	Мосин Сергей Геннадьевич	ru_RU
dc.date.accessioned	2022-01-01T00:00:00Z	ru_RU
dc.date.available	2022-01-01T00:00:00Z	ru_RU
dc.date.issued	2022	ru_RU
dc.identifier.citation	Matyukha V, Voloshchuk S, Mosin S., A Configurable IP Core for Calculating the Integer Square Root for Serial and Parallel Implementations in FPGA//Electronics (Switzerland). - 2022. - Vol.11, Is.15. - Art. №2335.	ru_RU
dc.identifier.uri	https://repository.kpfu.ru/?p_id=270395	ru_RU
dc.description.abstract	Electronics (Switzerland)	ru_RU
dc.description.abstract	The development of digital technologies is in many ways associated with an improvement of integrated technologies, microelectronic components, and the capabilities of hardware accelera-tion of the most computationally complex operations. Field-programmable gate arrays (FPGAs) are actively used for prototyping or the small-scale production of special purpose digital signal processing (DSP) devices. The implementation of DSP algorithms is variative in nature and affects important indicators of a produced device, such as the accuracy of the numerical solution, per-formance, structural/functional complexity, etc. The architectural features of the FPGA can be used for choosing an effective DSP algorithm in the form of solving the multicriteria discrete optimi-zation problem. This paper analyzes and selects an effective algorithm for calculating the integer square root, which is one of the most frequently used digital signal processing operations. A behavioral model based on a non-restoring algorithm is presented. The SystemVerilog description of the module for calculating the square root, presented in the form of a universal configurable IP core, has been developed and synthesized. The configuration allows one to change the width of the input data bus and select the serial or parallel processing mode for scalar or vector data. The results of testing and comparison of the obtained characteristics with the corresponding Xilinx Cordic IP core are presented. The field test of the proposed IP core implemented in the Xilinx FPGA SOC xc7z045ffg900-2 has demonstrated the gain in the maximum system frequency at 174 MHz in the sequential mode with a 48-bit input bus and 169 MHz in the pipelined mode at a reduction of both the structural complexity and the number of used FPGA internal resources in comparison with the Xilinx Cordic IP core.	ru_RU
dc.language.iso	ru	ru_RU
dc.subject	integer square root	ru_RU
dc.subject	non-restoring algorithm	ru_RU
dc.subject	FPGA design	ru_RU
dc.subject	pipelined data processing	ru_RU
dc.title	A Configurable IP Core for Calculating the Integer Square Root for Serial and Parallel Implementations in FPGA	ru_RU
dc.type	Статьи в зарубежных журналах и сборниках	ru_RU